-- Vhdl test bench created from schematic C:\Users\Tom\Documents\lcpd-scope\vhdl\project\AD_Schematic.sch - Sun Jun 06 14:50:03 2010
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--LIBRARY UNISIM;
--USE UNISIM.Vcomponents.ALL;
ENTITY AD_Schematic_AD_Schematic_sch_tb IS
END AD_Schematic_AD_Schematic_sch_tb;
ARCHITECTURE behavioral OF AD_Schematic_AD_Schematic_sch_tb IS 

   COMPONENT AD_Schematic
   PORT( reset_in	:	IN	STD_LOGIC; 
          divider_in	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          CLK_In	:	IN	STD_LOGIC; 
          Enable_in	:	IN	STD_LOGIC; 
          Data_a	:	IN	STD_LOGIC_VECTOR (11 DOWNTO 0); 
          Data_b	:	IN	STD_LOGIC_VECTOR (11 DOWNTO 0); 
          Trigger_level_in	:	IN	STD_LOGIC_VECTOR (11 DOWNTO 0); 
          Trigger_Mode_in	:	IN	STD_LOGIC; 
          Trigger_Edge_in	:	IN	STD_LOGIC; 
          Trigger_A_B_in	:	IN	STD_LOGIC; 
          n_samples_in	:	IN	STD_LOGIC_VECTOR (10 DOWNTO 0); 
          n_presamples_in	:	IN	STD_LOGIC_VECTOR (10 DOWNTO 0); 
          ram_we	:	OUT	STD_LOGIC; 
          ram_ena	:	OUT	STD_LOGIC; 
          ram_clk	:	OUT	STD_LOGIC; 
          wb_trigger	:	OUT	STD_LOGIC; 
          ram_adr	:	OUT	STD_LOGIC_VECTOR (11 DOWNTO 0); 
          ram_data	:	OUT	STD_LOGIC_VECTOR (31 DOWNTO 0);
			 newdata_test1 : OUT STD_LOGIC);
   END COMPONENT;

   SIGNAL reset_in	:	STD_LOGIC;
   SIGNAL divider_in	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL CLK_In	:	STD_LOGIC;
   SIGNAL Enable_in	:	STD_LOGIC;
   SIGNAL Data_a	:	STD_LOGIC_VECTOR (11 DOWNTO 0);
   SIGNAL Data_b	:	STD_LOGIC_VECTOR (11 DOWNTO 0);
   SIGNAL Trigger_level_in	:	STD_LOGIC_VECTOR (11 DOWNTO 0);
   SIGNAL Trigger_Mode_in	:	STD_LOGIC;
   SIGNAL Trigger_Edge_in	:	STD_LOGIC;
   SIGNAL Trigger_A_B_in	:	STD_LOGIC;
   SIGNAL n_samples_in	:	STD_LOGIC_VECTOR (10 DOWNTO 0);
   SIGNAL n_presamples_in	:	STD_LOGIC_VECTOR (10 DOWNTO 0);
   SIGNAL ram_we	:	STD_LOGIC;
   SIGNAL ram_ena	:	STD_LOGIC;
   SIGNAL ram_clk	:	STD_LOGIC;
   SIGNAL wb_trigger	:	STD_LOGIC;
   SIGNAL ram_adr	:	STD_LOGIC_VECTOR (11 DOWNTO 0);
   SIGNAL ram_data	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
	SIGNAL newdata_test1 : STD_LOGIC;
BEGIN

   UUT: AD_Schematic PORT MAP(
		reset_in => reset_in, 
		divider_in => divider_in, 
		CLK_In => CLK_In, 
		Enable_in => Enable_in, 
		Data_a => Data_a, 
		Data_b => Data_b, 
		Trigger_level_in => Trigger_level_in, 
		Trigger_Mode_in => Trigger_Mode_in, 
		Trigger_Edge_in => Trigger_Edge_in, 
		Trigger_A_B_in => Trigger_A_B_in, 
		n_samples_in => n_samples_in, 
		n_presamples_in => n_presamples_in, 
		ram_we => ram_we, 
		ram_ena => ram_ena, 
		ram_clk => ram_clk, 
		wb_trigger => wb_trigger, 
		ram_adr => ram_adr, 
		ram_data => ram_data,
		newdata_test1 => newdata_test1
   );

  -- Clock process definitions
   CLK_In_process :process
   begin
		CLK_In <= '0';
		wait for 5 ns;
		CLK_In <= '1';
		wait for 5 ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
      Data_a <= "101010101010";	
		Data_b <= "010101010101";
		reset_in <= '0';
		divider_in <= "00000000";
		Enable_in <= '1';
		Trigger_level_in <= "101010101011";
		Trigger_Mode_in <= '0'; 
		Trigger_Edge_in <= '1'; --rising edge
		Trigger_A_B_in <= '1'; -- Channel A
		
		n_samples_in <= "00000000010";
		n_presamples_in <="00000000001"; 
      wait for 100 ns;

      -- insert stimulus here 

      wait;
   end process;


END;
